Use of Op-Amp In Data Converters

Use of Op amp in Data Converters

 

Introduction

      In Nature signals can be analog or digital. Sometimes we need to convert analog signal into digital equivalent and vice versa, the electronics circuits used for such a conversion area called as data converters.

      Due to the many advantages offered by the digital systems, they are widely used in many fields such as instrumentation, computers, communication and control, in many such applications the signals are not available in digital form, most of the physical quantities such as temperature, pressure, displacement, vibrations etc. are available in analog form. These quantities are represented accurately in analog form but it is difficult to process, store or transmit the analog signal because error gets introduced easily, due to noise.

      Hence to reduce these errors, it is always better to express these physical quantities in the digital form. The digital representation of an analog signal makes strong possible, processing simpler and transmission of such signal easier.

      Therefore, analog to digital conversion is necessary. now once the processing, transmission etc. is done the signal should be back to its analog form, for which the digital to analog conversion is essential and is implemented.

      Both analog to digital (A to D) and digital to analog (D to A) circuits are called as Data converters and they are available in the IC form.

Why do I need Op Amp for data converters ?

Figure 1

Op amps are often used as drivers for ADCs to provide the gain and level-shifting required for the input signal to match the input range of the ADC. An op amp may be required because of the requirements of antialiasing filter impedance matching. In some cases, the antialiasing filter may be an active filter and include op amps as part of the filter itself

      In the case of DACs, some have voltage output, some have current output. The output might be very weak and cannot drive any substantial load. Since an op-amp takes virtually no current inside, and can drive strong loads, the op-amp is used to buffer the weak DAC output to drive much stronger loads.

Types of Data Converters

The data converters are basically two types:

1.       Digital to Analog Converters (DACs)

2.       Analog to Digital Converters (ADCs)

The classification of data converters is shown in the figure below:

Figure 2

Types of Digital to Analog Converters -

1. Binary Weighted Resistor DAC

In the weighted resistor type DAC, each digital level is converted into an equivalent analog voltage or current.
The following figure shows the circuit diagram of the binary weighted resistor type DAC.

Figure 3

It consists of parallel binary weighted resistor bank and a feedback resistor Rf.
The switch positions decides the binary word ( i.e. B1 B2B3…Bn ).
In the circuit op-amp is used as current to voltage converter.

Analysis:
Let us analyse the circuit using normal analysis concepts used in op-amp. When the switches are closed the respective currents are flowing through resistors as shown in the circuit diagram above.
Since input current to the op-amp is zero, the addition current flows through feedback resistor.
∴I=I1+I2+I3+ …………+In
The inverting terminal of op-amp is virtually at ground potential.

If the reference voltage is positive i.e. + VR, then the output voltage is positive.

Consider the example of 3-bit DAC, and for the different combination digital inputs, the analog output voltage Vo is calculated as shown in figure 4. And figure 5 shows the staircase output voltage waveform obtained for R-2R ladder DAC (when VR is positive).

                                 Figure 4                                                                                                   

                                                                                           Figure 5

            2.        IR-2R Ladder DAC

The following circuit diagram shows the basic 2 bit R-2R ladder DAC circuit using op-amp. Here only two values of resistors are required i.e. R and 2R. The number of digits per binary word is assumed to be two (i.e. n = 2). The switch positions decides the binary word ( i.e. B1 B0 ).

The typical value of feedback resistor is Rf = 2R. The resistance R is normally selected any value between 2.5 kΩ to 10 kΩ.

The operation of the below ladder type DAC (Figure 6) is explained with the binary word (B1B0= 01), the circuit shown in Figure 6 can be drawn as shown in Figure 7 .

The generalized analog output voltage equation can be given as

Applying the nodal analysis concept at point (A) and point (B), we gets following equations

  

Substituting the equation of VB in the above equation, we get

The voltage at point A i.e. VA is applied as input to the op-amp which is in inverting amplifier mode as shown in figure below.

The output voltage of the complete setup
∴Vo=-(2R/R) VA

∴Vo=-(2R/R)(-VR/8)

∴Vo=VR/4

Similarly for other three combinations of digital input the analog output voltage Vo is calculated as follows

Types of Analog to Digital Converters -

        1.       Flash Type ADC

Flash Type ADC is based on the principle of comparing analog input voltage with a set of reference voltages.

To convert the analog input voltage into a digital signal of n-bit output, (2ⁿ – 1) comparators are required.

The following figure shows 2- bit flash type ADC

The three op-amps are used as comparators. The non-inverting inputs of all the three comparators are connected to the analog input voltage. The inverting terminals are connected to a set of reference voltages (V/4), (2V/4) and (3V/4) respectively which are obtained using a resistive divider network and power supply +V.

The output of the comparator is in positive saturation(i.e. logic 1), when voltage at non-inverting terminal is greater than voltage at inverting terminal and is in negative saturation otherwise.

The following table shows the comparator outputs for different ranges of analog input voltages and their corresponding digital outputs.

Consider first condition, where analog input voltage VA is less than (V/4). In this case, the voltage at the non-inverting terminals of all the three comparators is less than the respective voltages at inverting terminals and hence the comparator outputs are C1C2C3 = 000.

This comparator outputs are applied to the further coding circuit to get the digital outputs as B1B0 = 00

Similarly the digital outputs are calculated for other three conditions also

        I.                  2. Counter type ADC

The counter type ADC is constructed using a binary counter, DAC and a comparator. The output voltage of a DAC is VD which is equivalent to corresponding digital input to DAC.
The following figure shows the n-bit counter type ADC.

Operation:

The n-bit binary counter is initially set to 0 by using reset command. Therefore the digital output is zero and the equivalent voltage VD is also 0V.

When the reset command is removed, the clock pulses are allowed to go through AND gate and are counted by the binary counter.

The D to A converter (DAC) converts the digital output to an analog voltage and applied as the inverting input to the comparator. The output of the comparator enables the AND gate to pass the clock.

The number of clock pulses increases with time and the analog input voltage VD is a rising staircase waveform as shown in figure below.

The counting will continue until the DAC output VD, equals and just rises more than unknown analog input voltage VA. Then the comparator output becomes low and this disables the AND gate from passing the clock.

The counting stops at the instance VA< VD, and at that instant the counter stops its progress and the conversion is said to be complete. 

Figure 11

The numbers stored in the n-bit counter is the equivalent n-bit digital data for the given analog input voltage.

        

       3.  Dual Slop type ADC

In dual slope type ADC, the integrator generates two different ramps, one with the known analog input voltage VA and another with a known reference voltage –Vref. Hence it is called a s dual slope A to D converter. The logic diagram for the same is shown below.

Operation:

The binary counter is initially reset to 0000; the output of integrator reset to 0V and the input to the ramp generator or integrator is switched to the unknown analog input voltage VA.

The analog input voltage VA is integrated by the inverting integrator and generates a negative ramp output. The output of comparator is positive and the clock is passed through the AND gate. This results in counting up of the binary counter.

The negative ramp continues for a fixed time period t1, which is determined by a count detector for the time period t1. At the end of the fixed time period t1, the ramp output of integrator is given by

∴VS=-VA/RC×t1

When the counter reaches the fixed count at time period t1, the binary counter resets to 0000 and switches the integrator input to a negative reference voltage –Vref.

Now the ramp generator starts with the initial value –Vs and increases in positive direction until it reaches 0V and the counter gets advanced. When Vs reaches 0V, comparator output becomes negative (i.e. logic 0) and the AND gate is deactivated. Hence no further clock is applied through AND gate. Now, the conversion cycle is said to be completed and the positive ramp voltage is given by

∴VS=Vref/RC×t2

Where Vref & RC are constants and time period t2 is variable.

The dual ramp output waveform is shown below.

Since ramp generator voltage starts at 0V, decreasing down to –Vs and then increasing up to 0V, the amplitude of negative and positive ramp voltages can be equated as follows.

∴Vref/RC×t2=-VA/RC×t1

∴t2=-t1×VA/Vref

∴VA=-Vref×t1/t2

 

Thus the unknown analog input voltage VA is proportional to the time period t2, because Vref is a known reference voltage and t1 is the predetermined time period.

The actual conversion of analog voltage VA into a digital count occurs during time t2. The binary counter gives corresponding digital value for time period t2. The clock is connected to the counter at the beginning of t2 and is disconnected at the end of t2. Thus the counter counts digital output as

Digital output=(counts/sec) t2

∴Digital output=(counts/sec)[t1×VA/Vref ]

For example, consider the clock frequency is 1 MHz, the reference voltage is -1V, the fixed time period t1 is 1ms and the RC time constant is also 1 ms. Assuming the unknown analog input voltage amplitude as VA = 5V, during the fixed time period t1 , the integrator output Vs is

∴VS=-VA/RC×t1=(-5)/1ms×1ms=-5V

During the time period t2, ramp generator will integrate all the way back to 0V.

∴t2=VS/Vref ×RC=(-5)/(-1)×1ms=5ms=5000μs

Hence the 4-bit counter value is 5000, and by activating the decimal point of MSD seven segment displays, the display can directly read as 5V.

       4.  Successive Approximation type ADC

Successive Approximation type ADC is the most widely used and popular ADC method. The conversion time is maintained constant in successive approximation type ADC, and is proportional to the number of bits in the digital output, unlike the counter and continuous type A/D converters. The basic principle of this type of A/D converter is that the unknown analog input voltage is approximated against an n-bit digital value by trying one bit at a time, beginning with the MSB. The principle of successive approximation process for a 4-bit conversion is explained here. This type of ADC operates by successively dividing the voltage range by half, as explained in the following steps.

(1) The MSB is initially set to 1 with the remaining three bits set as 000. The digital equivalent voltage is compared with the unknown analog input voltage.

(2) If the analog input voltage is higher than the digital equivalent voltage, the MSB is retained as 1 and the second MSB is set to 1. Otherwise, the MSB is set to 0 and the second MSB is set to 1. Comparison is made as given in step (1) to decide whether to retain or reset the second MSB.

The above steps are more accurately illustrated with the help of an example.

Let us assume that the 4-bit ADC is used and the analog input voltage is VA = 11 V. when the conversion starts, the MSB bit is set to 1.

Now VA = 11V > VD = 8V = [1000]2

Since the unknown analog input voltage VA is higher than the equivalent digital voltage VD, as discussed in step (2), the MSB is retained as 1 and the next MSB bit is set to 1 as follows

VD = 12V = [1100]2

Now VA = 11V < VD = 12V = [1100]2

Here now, the unknown analog input voltage VA is lower than the equivalent digital voltage VD. As discussed in step (2), the second MSB is set to 0 and next MSB set to 1 as

VD = 10V = [1010]2

Now again VA = 11V > VD = 10V = [1010]2

Again as discussed in step (2) VA>VD, hence the third MSB is retained to 1 and the last bit is set to 1. The new code word is

VD = 11V = [1011]2

Now finally VA = VD , and the conversion stops.

The functional block diagram of successive approximation type of ADC is shown below.

It consists of a successive approximation register (SAR), DAC and comparator. The output of SAR is given to n-bit DAC. The equivalent analog output voltage of DAC, VD is applied to the non-inverting input of the comparator. The second input to the comparator is the unknown analog input voltage VA. The output of the comparator is used to activate the successive approximation logic of SAR.

When the start command is applied, the SAR sets the MSB to logic 1 and other bits are made logic 0, so that the trial code becomes 1000.